1. Field of the Invention
Generally, the present disclosure relates to the field of semiconductor processing, and, in particular, to techniques for the processing of semiconductor wafers wherein wafer handling elements touching wafers are employed.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements which include, in particular, field effect transistors. The circuit elements in an integrated circuit may be electrically connected by means of electrically conductive metal lines formed in a dielectric material, for example, by means of damascene techniques. The electrically conductive metal lines may be provided in a plurality of interconnect layers that are stacked on top of each other above a substrate in and on which the circuit elements are formed. Metal lines in different interconnect layers may be electrically connected with each other by means of contact vias that are filled with metal.
For the formation of integrated circuits, techniques of photolithography may be used. For performing photolithography, a layer of a photoresist may be formed on a wafer. This may be done by means of techniques of spin coating. In spin coating, a photoresist solution that includes a photoresist and a solvent may be dispensed to a surface of a wafer that is mounted on a wafer chuck. The photoresist solution may be distributed over the surface of the wafer by rotating the wafer. The wafer may be rotated at a relatively high speed of rotation for an amount of time until a substantial amount of the solvent of the photoresist solution has evaporated and a solid layer of the photoresist remains on the surface of the wafer. In addition to the photoresist layer, other coating layers, such as, for example, optical planarization layers (OLP layers), bottom anti-reflective coatings (BARCs), top anti-reflective coatings (TARCs) and immersion top coats which may be formed over photoresist layers for protecting the photoresist from an immersion fluid used in immersion photolithography and vice versa, may be formed on the wafer, for example, by means of spin coating.
Before the formation of the layer of photoresist, a pre-treatment of the wafer may be performed, which may include a dehydration baking, wherein the wafer is heated to an elevated temperature, and/or a vapor priming, wherein the wafer is exposed to an adhesion promoting agent. The dehydration baking and/or vapor priming may improve an adhesion of the photoresist to the wafer.
After the formation of the layer of photoresist, an edge bead removal process and/or an edge exposure process may be performed for removing relatively thick portions of photoresist (so-called “edge beads”) from the edge of the wafer, and a pre-exposure bake wherein the wafer is heated may be performed.
Thereafter, the photoresist may be exposed by projecting a photomask (sometimes also denoted as “reticle”) to the layer of photoresist in an exposure tool, for example, in a so-called scanner. In doing so, portions of the photoresist are irradiated with actinic light, i.e., light that induces a chemical reaction in the photoresist by which the solubility of the photoresist in a subsequent development process is substantially changed, for example, ultraviolet light, which is used for projecting the photomask to the photoresist. Other portions of the photoresist are not irradiated, wherein the pattern of irradiated portions of the photoresist depends on a pattern of photomask features provided on the photomask.
Thereafter, a post-exposure bake wherein the wafer is heated may be performed, and the photoresist may be developed to form a photomask. Depending on whether a negative or a positive photoresist is used, and whether a negative or positive development process is used, in the development process, either the non-irradiated portions or the irradiated portions of the photoresist are dissolved in a developer and, thus, are removed from the wafer.
After the formation of the developed photoresist layer, processes for patterning the wafer or modifying the electrical or chemical properties of the wafer may be performed using the portions of the photoresist remaining on the wafer as a photoresist mask. The processes for patterning the wafer may include one or more etch processes, wherein material is removed from portions of the wafer that are not covered by the photoresist mask. Thus, features may be formed on the wafer. The processes for modifying the electrical or chemical properties of the wafer may include one or more ion implantation processes, wherein ions are implanted into portions of the wafer that are not covered by the photoresist mask.
In some applications, several tools used for the above-mentioned wafer processing that is performed before the exposure of the photoresist and tools for the wafer processing that is performed after the exposure of the photoresist may be integrated into larger systems which are called “photolithography tracks.” Photolithography tracks may include tools for performing various wafer processing techniques as described above, for example, coating tools, hot plates for performing bake processes wherein the wafer is heated and development tools that are used for supplying a developer solution to the wafers. The term “unit” is often used for a tool included in a photolithography track.
Additionally, photolithography tracks may include equipment for automatically moving wafers within the photolithography tracks. Within the units of a photolithography track, lift pins may be provided for lifting wafers from wafer supports on which the wafers are provided during the processing of the wafers in the tool, and robot arms may be used for transporting the wafers between the units. Typically, robot arms can grip a wafer in a state wherein the wafer has been lifted from the wafer support by means of the lift pins, and they can place wafers on the lift pins before the processing of the wafers.
Photolithography tracks may include up to about 80 units. Process flows performed at wafers in photolithography tracks may include from about 12 process steps to about 25 process steps, wherein up to about 4 units may be provided in parallel for each process step.
Lift pins and/or other wafer handling elements touching wafers that are provided in a photolithography track, such as, for example, robot arms and/or wafer clamps, may cause yield issues, which may include direct yield issues such as scratches formed on a backside of a wafer and implicit yield issues such as a greater likelihood of a formation of defective integrated circuits at a location on a front side of a wafer that is opposite to a location on a backside of the wafer touched by a wafer handling element.
Due to the relatively large number of wafer processing steps performed in a photolithography track, a wafer may be touched by a number of wafer handling elements that are provided in different units of the photolithography track and/or by different robot arms. Therefore, identifying a wafer handling element that causes yield issues and/or identifying a unit of a photolithography track wherein a wafer handling element causing yield issues is located may have issues associated therewith. In particular, identifying a unit causing yield issues that occur only intermittently may be relatively difficult. Known techniques include commonality experiments, wherein the processing of a relatively large number of wafers by a photolithography track is monitored, and correlations between units of the photolithography track and yield issues occurring are identified.
The present disclosure provides methods, systems and photolithography tracks that may help to substantially avoid or at least reduce some or all of the above-mentioned issues.